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— Even the most advanced platforms are limited by the memory wall when dealing with data-centric applications

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Our solution

UPMEM PIM consists of thousands of innovative data processors (DPU) uniquely positioned within the DRAM memory chips and next to the data, to compute data-intensive operations while drastically reducing off-chip data movements. Those DPUs are under the control of the high-level application running on the main CPU that ensures task orchestration.[/vc_column_text][/vc_column_inner][/vc_row_inner][vc_empty_space height=”80px”][vc_single_image image=”13316″ img_size=”full” alignment=”center”][/vc_column][/vc_row][vc_row][vc_column][ultimate_modal modal_title=”Request our technology white paper” btn_text=”Request our technology white paper” overlay_bg_opacity=”80″ img_size=”80″]

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UPMEM PIM solution demonstrated major benefits.

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Efficient

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15x better performance than CPU, 10x better TCO than CPU, GPU or FPGA solution while much faster! PIM servers consume about 10x less energy.

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Scalable

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The number of PIM units grows proportionally with memory capacity (DIMM channels/slots for servers), with no change in memory processes.

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Programmable

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Easy integration with high level applications.  PIM units are programmable with standard tools and skillset.

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Smooth integration

[/vc_column_text][vc_column_text css=”.vc_custom_1600678951857{padding-right: 50px !important;}”]Our unique design preserves current architectures. Only a BIOS update is required.[/vc_column_text][vc_separator color=”custom” align=”align_left” border_width=”2″ el_width=”30″ accent_color=”#f0e642″][/vc_column][/vc_row][vc_row full_width=”stretch_row_content_no_spaces” full_height=”yes” equal_height=”yes”][vc_column css=”.vc_custom_1527499676616{padding-bottom: 50px !important;background-color: #f0e642 !important;}”][vc_column_text css=”.vc_custom_1589375093088{padding-top: 2% !important;padding-right: 16% !important;padding-bottom: 2% !important;padding-left: 16% !important;}”]

UPMEM PIM introduces important features behind the acceleration of datacenters 

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A wide range of instruction set for various types of calculation

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Up to 2560 PIM units can be combined in a single socket server with 256GB PIM DRAM

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2,5 Tera bytes per second of memory bandwidth

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Roughly equivalent to 15 additional x86, with the main CPU used for orchestration

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Best performance per area processor

UPMEM DPU processor is delivering the best effective performance per mm2, compared to the latest RISC and CISC processors of the market, and is the only processor that can be routed in a memory chip.

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A technical exploit

Designing a RISC processor that can be fabbed with a DRAM memory process is a true technical exploit. Today numerous applications are developed to leverage the power of UPMEM PIM’s products.

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Co-processing model/smooth integration

This model of programmable co-processors in C (or RUST) language is versatile and enables a large number of use cases. The PIM units can be programmed one by one or by group, and process their local data independently from each other.

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C coding and no OS

The UPMEM DPU processor is programmable in C or RUST, thanks to its Software Development Kit (SDK), and does not require an OS. It is structurally secure and immune to row hammer attacks

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