Even the most advanced platforms are limited by the memory wall when dealing with data-centric applications

Our solution

UPMEM PIM consists of thousands of innovative data processors (DPU) uniquely positioned within the DRAM memory chips and next to the data, to compute data-intensive operations while drastically reducing off-chip data movements. Those DPUs are under the control of the high-level application running on the main CPU that ensures task orchestration.

The PIM reference platform

Intel Server Configuration with 20 PIM DIMM Modules


INTEL Server System R2312WFTZSR (2U)


INTEL Xeon Silver 42xx


4x32/64 GB DDR4-2666 RDIMM Dual Rank DRAM per socket


20 DDR4-2400 PIM modules

160 GB PIM memory


2560 @450 MHz

Memory Bandwidth

2,56 TB/s


INTEL SSD 2.0 TB 4-lane PCIe 3.0 QLC

Start programming using your own PIM server and leverage unprecedented memory bandwidth and computing power. Each UPMEM PIM DIMM contains 128 DPUs each communicating at 1GB/s with their 64 MB of memory for a total of 160 GB of PIM memory. The DPU is a 24 threads, 32-bit RISC processor – with 64-bit capabilities – working at 450Mhz (soon 600Mhz). A dual socket cascade lake server totalizes up to 2560 DPUs while the upcoming Ice Lake platform will welcome up to 28 PIM DIMMS, that is 3584 DPUs. Connect with us to discuss your target PIM server or to experiment remotely through our PIM data center.

UPMEM PIM solution demonstrated major benefits.



15x better performance than CPU, 10x better TCO than CPU, GPU or FPGA solution while much faster! PIM servers consume about 10x less energy.



The number of PIM units grows proportionally with memory capacity (DIMM channels/slots for servers), with no change in memory processes.



Easy integration with high level applications.  PIM units are programmable with standard tools and skillset.


Smooth integration

Our unique design preserves current architectures. Only a BIOS update is required.

UPMEM PIM introduces important features behind the acceleration of datacenters


General-purpose processor​

A wide range of instruction set for various types of calculation


Massively parallel​

Up to 2560 PIM units can be combined in a single socket server with 256GB PIM DRAM​

Larger bandwidth​

2,5 Tera bytes per second of memory bandwidth​

Extra computing power​

Roughly equivalent to 15 additional x86, with the main CPU used for orchestration​


Best performance per area processor

UPMEM DPU processor is delivering the best effective performance per mm2, compared to the latest RISC and CISC processors of the market, and is the only processor that can be routed in a memory chip.

A technical exploit

Designing a RISC processor that can be fabbed with a DRAM memory process is a true technical exploit. Today numerous applications are developed to leverage the power of UPMEM PIM’s products.


Co-processing model/smooth integration

This model of programmable co-processors in C (or RUST) language is versatile and enables a large number of use cases. The PIM units can be programmed one by one or by group, and process their local data independently from each other.

C coding and no OS

The UPMEM DPU processor is programmable in C or RUST, thanks to its Software Development Kit (SDK), and does not require an OS. It is structurally secure and immune to row hammer attacks

 Row Hammer prevention IP

Understand DRAM Row Hammer major threat

The Row Hammer attack, whether intentional or not, flips bits by rapidly and repeatedly accessing specific DRAM rows, creating security and reliability breaches for any connected device: server, PC, phone… Mitigations proposed by memory or processor makers as well as software developers have proved ineffective. It is thus  imperative to solve the problem, whether for standard DRAM or for PIM-DRAM.

How about building reliable and fully secure DRAM with UPMEM ROW Hammer suppression patented IP ?

Row Hammer fully provable prevention

UPMEM proposes a fully deterministic and provable Row Hammer solution, based on an innovative algorithm (a.k.a. Silver Bullet: see UPMEM’s U.S. patent 10,885,966-B1) and UPMEM’s experience in implementing logic in DRAM. This ultimate Row Hammer solution can tackle the most sensitive DRAM characteristics (very low MACs and high blast radius) at neglectable costs.
Silver Bullet is:
– Mathematically proven (proof available under NDA)
– Suitable to classical DRAMs and PIM enhanced DRAM