— Even the most advanced platforms are limited by the memory wall when dealing with data-centric applications
UPMEM PIM consists of thousands of innovative data processors (DPU) uniquely positioned within the DRAM memory chips and next to the data, to compute data-intensive operations while drastically reducing off-chip data movements. Those DPUs are under the control of the high-level application running on the main CPU that ensures task orchestration.
UPMEM PIM solution demonstrated major benefits.
UPMEM PIM introduces important features behind the acceleration of datacenters
A wide range of instruction set for various types of calculation
Up to 2560 PIM units can be combined in a single socket server with 256GB PIM DRAM
2,5 Tera bytes per second of memory bandwidth
Extra computing power
Roughly equivalent to 15 additional x86, with the main CPU used for orchestration
Best performance per area processor
UPMEM DPU processor is delivering the best effective performance per mm2, compared to the latest RISC and CISC processors of the market, and is the only processor that can be routed in a memory chip.
A technical exploit
Designing a RISC processor that can be fabbed with a DRAM memory process is a true technical exploit. Today numerous applications are developed to leverage the power of UPMEM PIM’s products.
Co-processing model/smooth integration
This model of programmable co-processors in C (or RUST) language is versatile and enables a large number of use cases. The PIM units can be programmed one by one or by group, and process their local data independently from each other.
C coding and no OS
The UPMEM DPU processor is programmable in C or RUST, thanks to its Software Development Kit (SDK), and does not require an OS. It is structurally secure and immune to row hammer attacks
Row Hammer prevention IP
Understand DRAM Row Hammer major threat
The Row Hammer attack, whether intentional or not, flips bits by rapidly and repeatedly accessing specific DRAM rows, creating security and reliability breaches for any connected device: server, PC, phone… Mitigations proposed by memory or processor makers as well as software developers have proved ineffective. It is thus imperative to solve the problem, whether for standard DRAM or for PIM-DRAM.
How about building reliable and fully secure DRAM with UPMEM ROW Hammer suppression patented IP ?
Row Hammer fully provable prevention
UPMEM proposes a fully deterministic and provable Row Hammer solution, based on an innovative algorithm (a.k.a. Silver Bullet: see UPMEM’s U.S. patent 10,885,966-B1) and UPMEM’s experience in implementing logic in DRAM. This ultimate Row Hammer solution can tackle the most sensitive DRAM characteristics (very low MACs and high blast radius) at neglectable costs.
Silver Bullet is:
– Mathematically proven (proof available under NDA)
– Suitable to classical DRAMs and PIM enhanced DRAM