The 1st Minisymposium on Applications and Benefits of UPMEM commercial Massively Parallel Processing-In-Memory Platform

August 28-29, 2023

Full day minisymposium at EURO-PAR 2023

Motivation and scope of the minisymposium

With the rise of data intensive applications in various fields, such as genomics, analytics and AI, the classical compute centric architecture reaches its limits. Communication between main memory and CPUs happens through a narrow bus with high latency, limited bandwidth, and most of the energy in the compute node is related to DRAM data-movement. The solution for this is to integrate powerful computing capabilities on the DRAM memory die, that is Processing-in-memory (PIM) DRAM.

As the first PIM architecture to be commercialized in real hardware, PIM architecture designed by UPMEM has received interest from many researchers, both academic and industrial. UPMEM PIM are pluggable in place of a regular DIMM. They offer massively parallel compute capabilities thanks to 8 simple processors (DPU) sitting on each DRAM chip that have extremely fast access to DRAM banks. A typical configuration totalises 2560 DPUs and can speed up applications up to tens of times.

This minisymposium gives the opportunity to understand how the technology can be used, how different applications can benefit from it, and the process of developing a PIM application, to anyone with a data intensive application to accelerate. Attendees will benefit from the feedback of industrial and academic researchers on their experience in porting applications in the field of genomics, analytics and AI. They will leave having gained a better understanding of the value of the technology to them and their ability to use it.

Target audience

Anyone with a data intensive application to accelerate can benefit from the minisymposium where they will have the opportunity to better understand the value of the technology, how it can be used and how to develop applications, thanks to the feedback of industrial and academic researchers on their experience in porting applications in the field of genomics, analytics and AI.

Integrators could also have the opportunity to understand how they can leverage the value of this technology for their customers.

Tentative agenda

09:00 – 09:05Session welcome and aimsUPMEM
09:05 – 10:00Keynote: UPMEM PIM platform for Data-Intensive ApplicationsYann FALEVOZ (UPMEM) /
10:00 – 10:30Invited talk: Understanding the potential of real processing-in-memory for modern workloadsJuan GOMEZ LUNA
10:30 – 11:00Coffee break
11:00 – 11:30Research paper: Processing-in-memory for Column-store WorkloadsNiloofar GHARAVI
11:30 – 12:00Invited talk: A Fast Processing-in-DIMM Join Algorithm Exploiting UPMEM DIMMsYoungsok KIM
(Yonsei University)
12:00 – 12:30Invited talk: PIM Performance and Economics for In-Memory DatabasesHanna KRUPPE
12:30 – 01:30Lunch Break
01:30 – 02:00Research paper: Processing-in-memory for Deep Learning Recommendation Model InferenceNiloofar ZARIF
02:00 – 02:30Research paper: A Programmable Look-up Table-based Processing in Memory Architecture for Massively Parallel, Energy-Efficient Processing of Data-intensive Applications within DRAMPurab Ranjan SUTRADHAR
02:30 – 03:00Keynote: UPMEM security architectureMassimiliano Bartoli
03:00 – 03:30Coffee break
03:30 – 04:00Research paper: Privacy-Preserving Computing on UPMEMElaheh SADREDINI
04:00 – 04:30Research paper: Banded Dynamic Programming Algorithms on UPMEM PIM ArchitectureMeven MOGNOL
(Univ. Rennes, CNRS-IRISA, Inria & UPMEM)
04:30 – 05:00Research paper: Protein Alignment on UPMEM PIM ArchitectureDominique LAVENIER
(Univ. Rennes, CNRS-IRISA & Inria)
05:00 – 05:15Conclusions and next stepsUPMEM


  • Julien LEGRIEL (UPMEM) – Julien Legriel holds an engineering degree and a Ph.D. in computer science from UGA and has 12 years of experience as a software engineer and technical leader. He worked in the Electronic Design Automation field, first at a startup and then at Synopsys, where he led a team working on software for RTL power optimization and analysis. Julien joined UPMEM in December 2020, he is now working as a technical leader on the SDK and applications on PIM.
  • Juan GOMEZ LUNA (ETH Zurich) – Juan Gómez-Luna is a senior researcher and lecturer at SAFARI Research Group @ ETH Zürich. He received the BS and MS degrees in Telecommunication Engineering from the University of Sevilla, Spain, in 2001, and the PhD degree in Computer Science from the University of Córdoba, Spain, in 2012.Between 2005 and 2017, he was a faculty member of the University of Córdoba. His research interests focus on processing-in-memory, memory systems, heterogeneous computing, and hardware and software acceleration of medical imaging and bioinformatics. He is the lead author of PrIM, the first publicly-available benchmark suite for a real-world processing-in-memory architecture, and Chai, a benchmark suite for heterogeneous systems with CPU/GPU/FPGA.
  • Niloofar GHARAVI (The University of British Columbia (UBC)) – Niloofar Gharavi is an active researcher at the Systopia Lab at the University of British Columbia, where she is pursuing a Masters of Applied Science in Computer Engineering under the supervision of Dr. Alexandra (Sasha) Fedorova. Prior to this, she obtained her Bachelor’s Degree with distinction from UBC. During her time as an undergraduate, she interned as a research engineer at the National Research Council of Canada. Her research interests include processing in memory, distributed systems, and memory subsystems.
  • Youngsok KIM (Yonsei University) – Youngsok Kim is currently an assistant professor with the Department of Computer Science at Yonsei University. His research interests include computer architecture and system software, with an emphasis on database acceleration, performance modeling and analysis, and next-generation CPU/GPU/NPU microarchitectures. In this presentation, he will present PID-Join, a fast processing-in-DIMM join algorithm designed and optimized for UPMEM DIMMs. PID-Join efficiently exploits the architectural characteristics of UPMEM DIMMs by prototyping single-IDP hash, sort-merge, and nested-loop join algorithms, bypassing CPU caches for accelerating all-to-all inter-IDP communication model, and taking advantage of the join operator’s loose constraint on its input and output tuples.
  • Hanna KRUPPE (SAP) – Hanna Kruppe is a third year PhD student working at SAP SE. Her research focuses on datacenter hardware for more efficient in-memory analytics, especially on PIM and the HANA database used in many of SAP’s products. SAP is one of the world’s leading producers of software for the management of business processes, developing solutions that facilitate effective data processing and information flow across organizations. Its broad portfolio of solutions is available on-premise and in the cloud. This includes hyperscale cloud vendors as well as SAP’s own infrastructure in dozens of data centers across the globe.
  • Niloofar ZARIF (The University of British Columbia (UBC)) – Niloofar Zarif is a graduate student at the University of British Columbia and she is curious about building customized systems that can increase the performance of Machine Learning workload. She is mainly interested in addressing Recommender Systems and has been working on using Processing-In-Memory for accelerating recommender systems for about 3 years. She also worked with the Merlin team at NVIDIA where she gained experience in building GPU-based recommender systems. Before joining UBC she gained research experience at the National University of Singapore and the Sharif University of Technology.
  • Purab Ranjan SUTRADHAR (Rochester Institute of Technology (RIT)) – Purab Ranjan Sutradhar received his Bachelor of Science (B.Sc.) in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 2017. He is pursuing his Ph.D. in Computer Engineering at Rochester Institute of Technology, Rochester, New York, USA. His research interest lies in memory-centric processing architectures and implementing various data-intensive and data-parallel applications, such as Deep Learning and Cryptography in memory-centric processors. He has primarily worked on designing and developing a DRAM-based processing-in-memory (PIM) architecture that utilizes a novel look-up-table (LUT) based computing technique for high-performance, energy-efficient AI acceleration and Data Encryption. He is also interested in developing large-scale memory-oriented computing systems for green data server and cloud computing applications. His other interests include hardware security of memory-centric processors and memory-centric security architectures.
  • Massimiliano BARTOLI (UPMEM) – Experienced security engineer, Massimiliano joined the team in September 2021. He is in charge of designing and leading the development of the next generation PIM security solution. Massimiliano has experiences in semiconductor companies such as Intel and NXP, where he led and has contributed to the development of ROM and firmware security solutions validated against security standards (i.e. FIPS 140-2 certification).
  • Elaheh SADREDINI (University of California, Riverside (UCR)) – Elaheh Sadredini is an Assistant Professor at the Department of Computer Science and Engineering at the University of California, Riverside (UCR). Her research broadly focuses on developing secure, high-performance, and energy-efficient architectures and particularly on enabling efficient IoT security with data-centric computing. Prior to joining UCR in 2020, she earned her Ph.D. in Computer Science from the University of Virginia in 2019. Her work has resulted in several publications at top-tier venues (such as MICRO, ISCA, ASPLOS, HPCA, DAC, ICS, ICCAD, and KDD) and patents. Elaheh is the recipient of several recognitions and awards, including the best paper award at the ACM International Conference on Computing Frontiers in 2016, the “Best of CAL” award in 2019, and a nomination for the best paper award at IISWC’19, FCCM’20, and HPCA’20. She was awarded the Hellman Fellowship from the University of California in 2022.
  • Meven MOGNOL (Univ. Rennes, CNRS-IRISA, Inria & UPMEM) – Meven Mognol is a PhD student, both part of the Genscale bioinformatics group at IRISA/Inria Rennes and the UPMEM Company at Grenoble since early 2022. His current research focuses on adapting alignment algorithms to the UPMEM Processing-in-memory architecture, which combines hardware, parallelization, and bioinformatics concerns.
  • Dominique LAVENIER (Univ. Rennes, CNRS-IRISA & Inria) – Dominique Lavenier is a senior CNRS (French National Center for Scientific Research) researcher and a member of the GenScale bioinformatics group at IRISA/Inria, Rennes, he created in 2012. His current research interests include bioinformatics, data structures, genomics, parallelism, processing-in-memory, and DNA storage. He is currently leading the French GenoPIM project whose goal is to investigate the parallelization of the main genomic algorithms on the UPMEM Processing-in-Memory architecture. He also participates in the European BioPIM project.

Workshop organizers


For any information, please contact Yann FALEVOZ: yfalevoz@upmem.com